The invention relates to a method of testing integrated circuits which are mounted on a carrier, a test pattern being serially applied for temporary storage to an integrated circuit, set to an input stage, by way of a first connection thereof, the integrated circuit subsequently being set to an execution state in order to form a result pattern from said test pattern, the result pattern being serially output by the integrated circuit, set to an output state, by way of a second connection thereof in order to form a characterization of correct/incorrect operation of the integrated circuit by checking the information content thereof. One example of such a carrier is provided with printed wiring (printed circuit board), but the invention is not restricted to such interconnection technology. As integrated circuits become more complex, the need for a reliable test method increases, because the rejection of a product during an early production phase is usually substantially less expensive than rejection during a later production phase. An integrated circuit can be thoroughly tested prior to mounting on such a carrier, so that the risk of a non-detected fault occurring in such an integrated circuit is negligibly small. However, it has been found that the testing of the carrier together with the mounted circuits in a structural test is useful, because an integrated circuit may be damaged during mounting and because an interconnection function may be faulty. A structural test checks whether given connections are present and operational, for example, whether two connections do not form a short-circuit. Functional aspects are not completely tested. The latter aspects may concern, for example, the high-frequency behavior of a circuit, fan-in/fan-out of parts and the like.
It is known to test combined, integrated circuits according to the "scan test" principle, for example as described in U.S. Pat. No. 3,761,695, in which the various integrated circuits are successively dealt with. According to the scan test principle, a number of bistable elements present in the integrated circuit are connected in a shift register in the input state and the output state, so that the test and result patterns can be serially input into and output from the shift register, respectively. In the execution state, these bistable elements are used as if the circuit were in normal operation. The principle described in the cited Patent can be extended to the "serpentine" concept described hereinafter with reference to FIG. 1. The drawbacks which limit the usability of this concept are also described. VLSI circuits, and machine-aided testing techniques therefor, are described in U.S. Pat. No. 4,656,592.